In reply to DVJoe:
In reply to ben@SystemVerilog.us:
Hi Ben,
Will the above solutions work if requests come in back to back. In the case of back to back requests, the $rose will not fire for the 2nd request, correct ?
At every clocking event there is an attempt at the assertion.
See my paper Understanding the SVA Engine,
https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2
If signal “a” is the sequence 0 0 1 1 1 0 1 1
All attempts where a==0 are vacuous.
In the above sequence you have 2 $rose(a) and with each of them a successful attempt.