In reply to feiphung:
Your formal verification approach does not seem correct; specifically:
[list=1]
[] Your assertions do not reflect the black-box requirements of the UART. They are rather written at the low-level of the testbench.
[] Since the DUT is the UART, your assertions need to reflect the requirements of the UART. They are typically in a module or a checker bound to the DUT.
[] What you should provide to the formal verification tool is the UART and the assertions (that are in module or a checker bound to the DUT).
[] What you submitted to the formal verification tool is the verification of the testbench with a UART. Not quite what you really want!
[/litestbench
See Assertions Instead of FSMs/logic for Scoreboarding and Verification | Verification Horizons | Verification Academy
Also, see All test code and test results used in that paper at
http://systemverilog.us/uart4hz.tar
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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