Hello all
I was trying out some example with the “static” keyword in SystemVerilog. I really got confused with the output.
module test;
class base;
int i;
// function get();
// static function get();
// function static get();
// static function static get();
int a;
a++;
$display(a);
endfunction
endclass
base b3 = new();
initial begin
base b1, b2;
b1 = new();
b2 = new();
b1.get();
b2.get();
b3.get();
end
endmodule
For “function get()” and “static function get()” i am getting output as
1
1
1
For “function static get()” and " static function static get()" i am getting output as
1
2
3
Q1) if a function is “static”, initialized before time 0. then how it is displayed as 1, 1, 1 for “static function get()”
Q2) In this “function static get()” method, my function is not static, but it is displayed as 1, 2, 3.
Q3)Difference between “static function get()”, “function static get()” and “static function static get()”