"Static" methods in Systemverilog

In reply to dave_59:

In reply to SriGanesh D:

function static get()
is illegal syntax. See What is the exact difference between static tasks/functions and automatic tasks/functions ? please explain with a clear example - SystemVerilog - Verification Academy

Hi Dave
Thanks for the reply, I got some idea about static and automatic methods. But one clarification, if “function static” is illegal syntax means. why didn’t tool show any error?