Slice "with - item"

SystemVerilog
,
1

hi,
i’m trying to write a coverpoint as follows:


covergroup cg with function sample (bit a, bit [31:0] d_in);
    c_c1:  coverpoint d_in iff (a==1){
        bins d_in_1[] = {['hd0000000:'hd0003def]} with (item [4:3] == 1);
    }

i’m getting the following error:
Hierarchical name component lookup failed at ‘item’.

can anyone see the problem?

thanks,
Gidon

2

In reply to gidon:

I believe you found a tool bug. Works for me in at least two other simulators. A workaround would be

      bins d_in_1[] = {['hd0000000:'hd0003def]} with (item ==? 'b1101_0000_0000_0000_????_????_???0_1???);
3

In reply to dave_59:
thanks Dave.

eventually I used this:


covergroup cg with function sample (bit a, bit [31:0] d_in);
    c_c1:  coverpoint d_in iff (a==1){
        bins d_in_1[] = {['hd0000000:'hd0003def]} with ((item & 'h00000018) == 1);
    }