Slice "with - item"

SystemVerilog
,
2

In reply to gidon:

I believe you found a tool bug. Works for me in at least two other simulators. A workaround would be

      bins d_in_1[] = {['hd0000000:'hd0003def]} with (item ==? 'b1101_0000_0000_0000_????_????_???0_1???);