Simulation closing as it hits illegal bin

SystemVerilog
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1

I am trying to implement functional coverage on error signal from RAM
The code :

covergroup basic_functions_cg;
CVP_LOCAL_BIST_ERROR_DETECT: coverpoint pkt.local_err_detect_sync[0] {
      bins value0 = {0};
      illegal_bins value1 = {1}; 
    }
endgroup

But as soon as local_err_detect_sync hit 1, the simulation end without executing remaining simulation

Error-[FCIBH] Illegal bin hit
/home/scratch.bshyam_methodology/shyam_nvtools/qa/mbist/mbist_logic/mbist_uvm/mbist_uvmtb/coverage_collector.sv, 147
$unit, “cbc_coverage::basic_functions_cg”
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 216000 ps, Illegal state
bin value1 of coverpoint CVP_LOCAL_BIST_ERROR_DETECT in covergroup
cbc_coverage::basic_functions_cg got hit with value 0x1
Covergroup Instance: top.me.obj.basic_functions_cg
Design hierarchy: $unit

How to rectify this situation? My intention is to capture error bit separately in coverage.

2

In reply to bachan21:

Hitting an illegal been means there is a problem with your testbench/coverage model. It was not meant to check functional behavior.

Stopping on an illegal bin hit might be a tool specific behavior. This Mentor/Siemens EDA sponsored public forum is not for discussing tool specific usage or issues. Please read your tool’s user manual or contact your tool vendor directly for support.