I am a hardware digital designer. I have been developing RTL-based soft IPs for more than 5 years in VHDL. Recently, designs are getting bigger and more sophisticated. I decided to adopt new techniques and methodologies for fast and efficient verification within the IPs since a while. However, when I decided to start learning HVL, it was a bit confusing for me. Therefore, I would appreciate your guidance very much.
I will try to describe my needs precisely, consequently you could provide me with the appropriate advice. I am developing several blocks in VHDL, then I want to combine these blocks to construct an IC for certain application. I want to develop a top level test-bench with SystemC including all the sub-blocks or the top block level of the application to perform efficient verification for the application top level. According to several discussions during workshops and conference, besides the internet search as well, I concluded that SystemC is a very powerful HVL. Therefore, I decide it to adopt for two reasons a) hardware abstract model “which can be used later on for verification”, b) TLM for verification. If I get it right, TLM is used to model the communication between the different sub-blocks within a design.
After I decided to use SystemC, I read about OVM and UVM for formal verification. However, they are both SystemVerilog based.
Now, I am confused. Is my choice to work with SystemC right for my needs “as explained before”?
Could you recommend/suggest to me, how can I start efficiently? I have read a lot on the net, watching several tutorials “Doulos, Aldec, and Verification Academy”, buy books “System Design with SystemC and Advanced Verification Techniques, A SystemC Approach for Successful Tapeout”. I still feel lost and not sure whether I am on the right way or not.
You could use SystemC, which would raise your level of abstraction and you would end up using TLM. SystemC is implemented in C++. SystemC tends to be used for system level modelling, but you could use it to build directed testbenches.
If you used OVM or UVM you would be using SystemVerilog as the underlying language. What SystemVerilog gives you over SystemC is the capability to use constrained random verification, covergroups and assertions all of which are useful to improve your productivity and the quality of your verification process.
If your primary purpose of choosing HVL is for HW Verification and don’t have legacy in it, I strongly recommend SystemVerilog with UVM over SystemC. Simply put - there is lot of momentum around this combination and tools tend to have better support for the same.
You might also want to ask yourself - can you not leverage on recent advancements in VHDL 2008 standard as starting step.
We recently assisted a similar customer in India. They use VHDL for all their designs (mostly FPGA, some ASICs) and TBs in VHDL. They traditionally don’t use heavy verification in pre-silicon but are getting to it largely due to extended debug time on the FPGA. Here is what we arrived at:
Use PSL/VHDL-08 for assertions & functional coverage (cover property).
Use advanced VHDL-08 techniques for extended testbnech techniques & modeling
The choice bet’n SV & VHDL finally came down to - why learn a new language when new VHDL (2008 version) can support many of what they needed. One thing that VHDL-08 doesn’t have yet is constrained random generation but Jim Lewis has a package for it, if interested.
Another factor was the commercial/business angle - VHDL simulator (with 2008 support) is enough than adding mixed language features/licenses.
Regards
Srini
Here is detailed agenda of what we covered during their team ramp-up: