If your primary purpose of choosing HVL is for HW Verification and don’t have legacy in it, I strongly recommend SystemVerilog with UVM over SystemC. Simply put - there is lot of momentum around this combination and tools tend to have better support for the same.
You might also want to ask yourself - can you not leverage on recent advancements in VHDL 2008 standard as starting step.
We recently assisted a similar customer in India. They use VHDL for all their designs (mostly FPGA, some ASICs) and TBs in VHDL. They traditionally don’t use heavy verification in pre-silicon but are getting to it largely due to extended debug time on the FPGA. Here is what we arrived at:
- Use PSL/VHDL-08 for assertions & functional coverage (cover property).
- Use advanced VHDL-08 techniques for extended testbnech techniques & modeling
The choice bet’n SV & VHDL finally came down to - why learn a new language when new VHDL (2008 version) can support many of what they needed. One thing that VHDL-08 doesn’t have yet is constrained random generation but Jim Lewis has a package for it, if interested.
Another factor was the commercial/business angle - VHDL simulator (with 2008 support) is enough than adding mixed language features/licenses.
Regards
Srini
Here is detailed agenda of what we covered during their team ramp-up: