Signed Multiplication Reference Model

SystemVerilog
1

Hi Everyone,

I have rtl module which calculates signed multiplication. Im getting proper result from the DUT. When verifying it in UVM, it is not matching the rtl result with reference model output, because, in reference model it is calculating unsigned multiplication.

How i can resolve that problem.

Thank In Advance,
Sunith

2

You will have understand how Verilog signed arithmetic works and most likely need to cast values to signed expressions. The default is usually to treat all bit vectors as unsigned. Maybe show some code and we can suggest how to modify it.

3

In reply to dave_59:

Hi Dave_59,

Thank you for your reply, I got the solution for it by my own.

Thank You