Signal name in Macro

SystemVerilog
,
1 

I am trying to have a Variable name in Macro, but it is throwing me error saying undefined variable name m_mst_3, Can anyone tell me what is the problem?

// Code your testbench here
// or browse Examples
// Examples of `define text macros


`define master(ARG1,ARG2) \
  ARG2 = m_mst_``ARG1;
  
   

module test;
  bit var_1;
  bit m_mst_``ARG1;
 
  initial begin
    
    
   // m_mst_``ARG1 = 1;
    
    `master(3,var_1);
    
  end
  
endmodule
2

In reply to rag123:

Two problems: Macro arguments (ARG1, ARG2) are only defined within the macro, and you can only use the `` token joining operator within the macro as well.

3

Hi Dave,
Can you show me an example of how to use it?

4

In reply to rag123:

I’m not sure what you’re trying to accomplish. But the following example works:

`define master1(ARG1,ARG2) \
  ARG2 = m_mst_``ARG1;
`define master2(ARG) \
    bit m_mst_``ARG; 

module test;
  bit var_1;
  `master2(3) 
  initial begin
 
 
   // m_mst_``ARG1 = 1;
 
    `master1(3,var_1);
 
  end
 
endmodule
5

In reply to dave_59:

Thanks Dave that helped :) one last question, Can we use the same ARG to define multiple bits? I tried this and it shows error. but when i tried with a separate define it worked.


// Code your testbench here
// or browse Examples
`define master1(ARG1,ARG2) \
  ARG2 = m_mst_``ARG1;
`define master2(ARG) \
    bit m_mst_``ARG  \
    bit b_mst_``ARG ;  
module test;
  bit var_1;
  `master2(3) 
  `
  //`master2(3)
  initial begin
  // m_mst_``ARG1 = 1;
   `master1(3,var_1)
  end
endmodule