Signal name in Macro

SystemVerilog
,
4

In reply to rag123:

I’m not sure what you’re trying to accomplish. But the following example works:

`define master1(ARG1,ARG2) \
  ARG2 = m_mst_``ARG1;
`define master2(ARG) \
    bit m_mst_``ARG; 

module test;
  bit var_1;
  `master2(3) 
  initial begin
 
 
   // m_mst_``ARG1 = 1;
 
    `master1(3,var_1);
 
  end
 
endmodule