Hope you are doing well,I have a question that if we want to make synthesizable design for N cycle delay of 32 bit signal at output then what will be the verilog code for this. I will really appreciate your answer
typedef logic [31:0] uint_t;
parameter N = 5;
wire uint_t in, out;
var uint_t fifo[N];
always @(posedge clk)
fifo[N-1] <= in;
for(genvar i=0;i<N-1;i++)
always @(posedge clk)
fifo[i] <= fifo[i+1];
assign out = fifo[0];
If N is not a parameter, you will have to define a maximum number of cycle delays for the size of the fifo, and then add a mux to select where the input to each stage of the fifo comes from.
typedef logic [31:0] uint_t;
parameter Max= 5;
int N;
wire uint_t in, out;
var uint_t fifo[N];
for(genvar i=0;i<Max;i++)
always @(posedge clk)
fifo[i] <= (i==(N-1))? in : fifo[i+1];
assign out = fifo[0];