Should driver/sequencer class name be different from object name?


I am facing a problem rekated to driver/sequencer class name.

If i try to create an object with the same name as that of their class names, I am getting an error. For example:

class ahbs_driver extends uvm_driver #(ahbs_transaction);

class ahbs_agent extends uvm_agent;
ahbs_driver ahbs_driver;



Above is giving me an error:
Error-[SV-EEM-SRE] Scope resolution error, 15
test, “ahbs_driver::type_id::create”
Target for scope resolution operator does not exist. Token ‘ahbs_driver’ is
not a class/package. Originating module ‘test’.
Check that class or package exists with referred token as the name

But if i change the name of the driver class to ahbs_driver1, the error goes off.

class ahbs_driver1 extends uvm_driver #(ahbs_transaction);

class ahbs_agent extends uvm_agent;
ahbs_driver1 ahbs_driver;



The same thing happens for sequencer also.
Please tell me what is the reason for such an error.


The reason is that it matters whether you are referring to the class or to an instance of the class. The compiler needs to know which you mean, so the names have to be different. This is also why you can’t name a signal in your design “module” or call a class “class”. You wouldn’t be able to name a function or task “ahbs_driver” either.
This is a SystemVerilog rule and is not specific to UVM.