Setting defualt sequence in run_phase of base test

UVM
,
1

Hi,

I created a base test inwhich I set the a defualt sequence in build phase as below.

class base_test extends uvm_test;

`uvm_component_utils(chip_base_test)

function new(string name = “base_test”, uvm_component parent = null);
super.new(name,parent);
endfunction : new

virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
uvm_config_db#(uvm_object_wrapper)::set(this,
“denali_mem_sequencer_h.run_phase”,
“default_sequence”,
den_mem_base_seq::type_id::get()
);
endfunction : build_phase

endclass

I create lot of tests which will be extended from this base_test

class test_1 extends base_test

Now I would like to have visibility of the above defualt sequence and seuqencer in run_phase of all child tests.
How can I set the default sequence in base_test such that it will be visible in run_phase of all child tests.

Thanks & Regards
Jayakumar

2

You should never set a default_sequence. The reason for this is that each test should have control over what sequence(s) are run. By specifying a default_sequence, you are eliminating this capability.

What you should do is have each test create() and start() the required sequences for that specific test. If there are common sequences used for configuration or initialization, create tasks in the base test that can be called from the run_phase() of each test.

3

In reply to cgales:

Hi,

Thanks for your response.
I would like to have a sequence for denali memory backdoor write and read access.
Hence I thought to place it in a dummy sequencer as default sequencer for denali memory sequence and using the p_sequencer (dummy_sequencer) in all of the child tests.
I just wanted to avoid each task call from each child test.

4

In reply to jkrishna:

I haven’t used Denali memory models lately, but I would expect that they support some UVM methods to read/write the memory contents directly. Have you asked the Denali support team how they recommend integrating memory accesses into your tests?

The default_sequence is designed to run a specific sequence on a specific sequencer at the start of simulation. It seems that you want to enable direct memory access which may or may not require a sequence/sequencer.

5

In reply to cgales:

Ok Thanks. I will check with Cadence.

My general question is about default sequence.

If I set a default sequence in a dummy sequencer in base test, how can this default sequence will be visible in all child tests which are all extended from base test?
Is it possible?

6

In reply to jkrishna:

Don’t use the default_sequence at all. Use the sequence start() mechanism in your tests.