In reply to jkrishna:
I haven’t used Denali memory models lately, but I would expect that they support some UVM methods to read/write the memory contents directly. Have you asked the Denali support team how they recommend integrating memory accesses into your tests?
The default_sequence is designed to run a specific sequence on a specific sequencer at the start of simulation. It seems that you want to enable direct memory access which may or may not require a sequence/sequencer.