Set flag when assertion fails or hold assertion failure reporting

[abhijain]

hi

is there a way in which i can hold the assertion failure reporting for some time,the scenario is as soon as my assertion failed i need to start 1 particular sequence and that sequence will start based on the event emitted after assertion failure,but what has happened is once assertion failed i can see event emmited but simulation ends and am not able to run my sequence

regards,
abhi

[user49]

*In reply to abhijain:*is there a way in which i can hold the assertion failure reporting for some time,the scenario is as soon as my assertion failed i need to start 1 particular sequence and that sequence will start based on the event emitted after assertion failure,but what has happened is once assertion failed i can see event emmited but simulation ends and am not able to run my sequence [/quote]
Few points:

1. When an assertion fails, you can set a flag in the testbench, e/g/.

bit flag;
ap: assert property(some_property) else flag <= 1'b1;  

2. Stopping the simulator depends upon the severity level you put in the action block.
   The severity levels can be specified by one of the following severity system tasks. The syntax for the severity message task is:

severity_message_task ::= fatal_message_task | nonfatal_message_task
fatal_message_task ::= $fatal [ ( finish_number [ , list_of_arguments ] ) ] ;
nonfatal_message_task ::= severity_task [ ( [ list_of_arguments ] ) ] ;
severity_task ::= $error | $warning | $info
finish_number ::= 0 | 1 | 2

3. By default, the severity of an assertion failure is “error”. For example:

$error represents a run-time error. Example:
ap_handshake : assert property ($rose(req) |=> ##[0:4] ack)
else $error ("%m @ time %0t, req = %0h, ack=%0h", $time, $sampled(req), $sampled (ack)); 

4. The simulation tool allows users to configure the behavior in response to an assertion failure. Maybe you have it configured to finish upon a failure.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

• SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
• A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
• Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
• Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
• Component Design by Example ", 2001 ISBN 0-9705394-0-1
• VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
• VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

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[abhijain]

In reply to ben@SystemVerilog.us:

thanks ben