Yes Sir I agree with you that sv code cannot be simply converted to uvm.
So I had developed whole testbench structure which is required for uvm i.e. active agent having driver, sequncer and monitor also scoreboard and environment. Everything is properly working with compilation clean. Now when I started writing testcase I got stuck into this thing as in sv code I was driving addr and data values from this task of interface which I had posted.
So now simply I just want to make a sequence through which register read write can be done without going into RAL as I am new to UVM.