Does UVM have any concept of a “semi-active” agent? Somewhere between passive and active, used in place of a passive agent, with the addition of nondestructive overriding of certain signals.
For example a semi-active agent on an AXI bus could randomly drive ARVALID/ARREADY signals to 0 occasionally. So long as the master sees the overridden ARREADY==0 and the slave sees the overridden ARVALID==0 the design should continue to work correctly with only a timing perturbation. This would give better control and coverage of lower levels of the design, without requiring a complete block-level testbench. (Though clearly it is no substitute for a proper block-level testbench.)
Assuming the concept is sound, there’s the matter of how to wire up such an agent so that it has these capabilities.
I’ve done similar thing using virtual sequencer/sequences and use an active driver/agent. I call it noise_generator - assuming we are talking about the same thing. Others call it “irritator” at times.
Srini, how did you wire in the active agent? The wires I want to control are connected to a DUT driver. I would need to either modify the RTL to insert my agent, or somehow use Verilog force/release to override the RTL driver.
Not sure if I understand you correctly - I used regular agent (with a SQR-DRVR) - just made a background sequence ticking along with main-line sequence via virtual sequence (for join_none of a forever loop inside bg_seq::body). Drop me a note via srini@cvcblr if you would like to see the example code.
For me your description is not clear, but I believe you do not need a ‘semi-active agent’. What should this be?
I assume you want to exercise bot legal values for ARREADY. Right. You can do this from your AXI agent.
What’s the problem?
I’m referring to an AXI bus connecting two blocks of RTL in my DUT. One block of RTL is master and another RTL block is slave. Normally I would connect a passive UVM agent to monitor this bus, not driving any signals.
An active UVM agent would apply when I have an RTL master or RTL slave, and the testbench drives the other end of that bus. Not the case here.
I want something in-between as I described in my first post. Most of the time, the RTL drives all signals, but occasionally I want the testbench to randomly insert some perturbations.
In reply to scottj97:
There are only 3 different types of agents:
(1) active
(2) re-active and
(3) passive
agents.
I guess you are looking for a re-active agent.
That clarifies quite a bit - my idea won’t work for this case. Perhaps you want to create a special driver-sqr-agent toggling only a subset of AXI signals and use force/release instead of regular drive. A more fancier way would be to create a wrapper interface with typical OE (output enable) used in bidir signals in RTL and use some muxing to drive the noise or the RTL.
I guess it boils down to how critical this testing is and how fancy you want to get