In reply to chr_sue:
I’m referring to an AXI bus connecting two blocks of RTL in my DUT. One block of RTL is master and another RTL block is slave. Normally I would connect a passive UVM agent to monitor this bus, not driving any signals.
An active UVM agent would apply when I have an RTL master or RTL slave, and the testbench drives the other end of that bus. Not the case here.
I want something in-between as I described in my first post. Most of the time, the RTL drives all signals, but occasionally I want the testbench to randomly insert some perturbations.