Yes it possible if you follow the right semantics. The default port direction for module ports is inout, and only wires can be connected to inout ports. What you need to do is construct the semaphore at the top level and pass a handle to the semaphore port as inputs to the module.
Would this work with generate loop as well, Dave?
Thanks.
module block_t (input logic clk, logic rst, semaphore s);
// Use semaphore before access to a shared bus
// Ex: assign bus = 5;
endmodule
module top_tb;
semaphore sem = new ();
genvar port_idx;
generate
for (port_idx = 0; port_idx < 8; port_idx++) begin : group
block_t block (core_clk, core_rst, sem);
end
endmodule : top_tb