In reply to ben@SystemVerilog.us:
I think it works without $changed(B_out) too. I didnt had such requirement.
If i use $changed(B_out) I need to be more careful with the range i provide in the second part.
If i’ve given ##[3:6] as below and if the signal propagated in less than 3 cycles it will fail as it expects to change within the window. Correct ?
I only had to check if the signal propagates, window was not necessary.
property CDC_prop;
logic v_temp;
@(posedge Clk_A) ($changed(A_in), v_temp = A_in) |=>
@(posedge Clk_B) 1’b1 ##[3:6]
($changed(B_out) && (B_out === v_temp));
endproperty:CDC_prop