Scoreboarding assertion for clock crossing signals

SystemVerilog
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4

In reply to amitr5:

On “Should’nt it be @(posedge dest_clock) instead of @(dest_clock) ?”
You are correct, my mistake. On

 property CDC_prop;
logic v_temp;
@(posedge Clk_A) ($changed(A_in), v_temp = A_in) |=>
@(posedge Clk_B) 1'b1 ##[2:3]
($changed(B_out) && (B_out === v_temp));
endproperty:CDC_prop
//looks OK to me.  
// Comment: from a requirement point of view, is the 
// ($changed(B_out) necessary?

Ben systemverilog.us