Sample an array of events and use it in SV bins

SystemVerilog
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1

Hi,
I intend to sample an array of events in an interface and then use elements in this array to fill bins in a covergroup.
The filled array will be available once all events have occurred.
I am attaching an equivalent code:

interface foo;
event foo_event[16];
endinterface: foo

module cov_foo(foo foo_if);
covergroup cvgp_foo;
cvgp1: coverpoint foo_if.foo_event{
bin b0 = foo_if.foo_event[0];
bin b1 = foo_if.foo_event[1];
…
bin b15 = foo_if.foo_event[15];
endgroup
endmodule

Basically I need to check if all 16 events have occurred or not and generate a coverage report of it.
This is not correct as its showing some errors but I don’t have any idea on how to implement this.
Any new ways are welcome.

Thanks,
Sarvesh

2

In reply to __SarVesH:

You are going to need to covert each event to a bit that gets set, and then cover each bit. Probably not a good idea to use events in the first place.