Runtime Error: vsim-3996 and vsim-3978

[babanrosesalluri5]

Hi all,

I had witten code for counter in UVM. As I am new to system verilog and UVM i had followed uvm_tutorial_for_candy_lovers_master code to implement counter in uvm. I had compiled uvm counter code in questasim 10.0c simulator and i found some run time errors as mentioned below. Can anyone help me out to resolve this errors.

run time error report:

vsim -novopt top

Refreshing D:\baban123_uvm\work.top

Refreshing D:\baban123_uvm\work.uvm_count_mod_8915_can_sv_unit

Loading sv_std.std

Loading mtiUvm.uvm_pkg

Loading work.uvm_count_mod_8915_can_sv_unit

Loading work.top

Refreshing D:\baban123_uvm\work.Bus_if

Loading work.Bus_if

Refreshing D:\baban123_uvm\work.Counter

Loading work.Counter

** Error: (vsim-3567) uvm_count_mod_8915_can.sv(345): No field named ‘start’.

Region: /uvm_count_mod_8915_can_sv_unit

** Error: (vsim-3567) uvm_count_mod_8915_can.sv(345): No field named ‘start’.

Region: /uvm_count_mod_8915_can_sv_unit

** Error: (vsim-3996) uvm_count_mod_8915_can.sv(345): Formal ‘start’ does not exist in call start.

Region: /uvm_count_mod_8915_can_sv_unit

** Error: (vsim-3978) uvm_count_mod_8915_can.sv(345): Cannot assign an unpacked type to a packed type.

Time: 0 ns Iteration: 0 Region: /uvm_count_mod_8915_can_sv_unit File: uvm_count_mod_8915_can.sv

Error loading design

/////////////////////////////////////////////////
/////////////////// code is here ////////////////////////////
///////////////////////////////////////////////
`include “uvm_macros.svh”
import uvm_pkg::;

module Counter(clk,reset,data);
input wire clk,reset;
output reg [3:0] data;

    always @ (posedge clk)
    begin
            if(reset)
               data<=0;
            else
            data<=data+1;
    end

endmodule: Counter definition

interface Bus_if;
wire clk;
wire reset;
reg [3:0] data;
endinterface:Bus_if

module top();

//generate the clock
reg clk = 0;
initial begin
forever #5 clk = ~clk;
end

//interface instance
Bus_if Bus_if1();

// Dut instance
Counter Counter1(Bus_if1.clk,Bus_if1.reset,Bus_if1.data);

//set virtual interface
initial begin
uvm_config_db#(virtual Bus_if)::set(null,“*”,“Bus_if1”,Bus_if1);
run_test();
end
endmodule: top

class counter_trans extends uvm_sequence_item;

    rand bit reset;
    rand bit data;

    function new(string name="");
    super.new(name) ;
    endfunction

    `uvm_object_utils_begin(counter_trans)
    `uvm_field_int ( reset,UVM_ALL_ON )
    `uvm_field_int ( data, UVM_ALL_ON )
    `uvm_object_utils_end

endclass:counter_trans //used for generating stimulus

//counter sequence definition is here
class count_seq extends uvm_sequence#(counter_trans);

    `uvm_object_utils(count_seq)

    virtual Bus_if Bus_if1;

    function new(string name="");
            super.new(name);
            void'(uvm_config_db#(virtual Bus_if)::get(this,"*","Bus_if1",Bus_if1));
            if(!uvm_config_db#(virtual Bus_if)::get(this,"* ","Bus_if1",Bus_if1))   begin
                    `uvm_error("","uvm_config_db::get failed in driver");
            end
    endfunction

    task body();
            counter_trans  req;
            req=counter_trans::type_id::create("req",this);

            if(Bus_if1.clk) begin
            start_item( req.randomize() );
            finish_item(req); 
            end
            else if (!req.randomize()) begin
            `uvm_error("MY_SEQUENCE", "Randomize failed.");
            end
    endtask

endclass:count_seq

//sequencer defination
class counter_sequencer extends uvm_sequencer # (counter_trans);
`uvm_component_utils(counter_sequencer)

    counter_sequencer        sqr;
    count_seq                seq;

    function new(string name="");
            super.new(name);
    endfunction

    task body();
    seq=count_seq::type_id::create("seq",this);
    fork
    seq.start(.counter_sequencer(sqr),.parent_sequence(this));
    join
    endtask

endclass:counter_sequencer

class driver extends uvm_driver # (counter_trans);
`uvm_component_utils(driver)

    virtual Bus_if Bus_if1;

    function new(string name,uvm_component_parent="null");
            super.new(name,null);
    endfunction

    function void build_phase(uvm_phase phase);
            super.build_phase(phase);
            void'(uvm_config_db#(virtual Bus_if)::get(this,"*","Bus_if1",Bus_if1));
            if(!uvm_config_db#(virtual Bus_if)::get(this,"* ","Bus_if1",Bus_if1))   begin
            `uvm_error("","uvm_config_db::get failed in driver");
            end
    endfunction

    task run_phase(uvm_phase phase);
            counter_trans req;
            forever begin
            seq_item_port.get_next_item(req);
            // gets the sequence item from the counter_trans
            if(Bus_if1.clk)
            Bus_if1.reset <= req.reset;
            Bus_if1.data  <= req.data;
            seq_item_port.item_done();
            end
    endtask

endclass:driver

class monitor extends uvm_monitor;

    `uvm_component_utils(monitor)

    uvm_analysis_port#(counter_trans) ap_objseq;

    virtual Bus_if Bus_if1;

    function new(string name, uvm_component_parent="null");
            super.new(name, null);
    endfunction

    function void build_phase(uvm_phase phase);
            super.build_phase(phase);
            void'(uvm_config_db#(virtual Bus_if)::get(this,"*","Bus_if1",Bus_if1));
            ap_objseq = new(.name("ap_objseq"),.parent(this));
    endfunction

    task run_phase(uvm_phase phase);
            forever begin
            counter_trans req;
            req=counter_trans::type_id::create("req",this);
            @ Bus_if1.clk;
            req.reset = Bus_if1.reset;
            req.data = Bus_if1.data;
            ap_objseq.write(req);
            end
    endtask

endclass:monitor

class coverage extends uvm_subscriber # (counter_trans);
`uvm_component_utils(coverage)
counter_trans req;

    covergroup count_cov;
            coverpoint req.reset;
            coverpoint req.data;
    endgroup

    function new(string name, uvm_component_parent="null");
            super.new(name,null);
            count_cov = new();
    endfunction

    function void write(counter_trans cov_tx);
            req = cov_tx;
            count_cov.sample();
    endfunction

endclass:coverage

typedef class scoreboard;

class counter_subscriber extends uvm_subscriber # (counter_trans);
`uvm_component_utils(counter_subscriber)

    function new (string name, uvm_component_parent="null");
            super.new(name, null);
    endfunction

    function void write(counter_trans sb_t);
   //         scoreboard cnt_sb;
            $cast(cnt_sb,m_parent);
            endfunction

endclass:counter_subscriber

class scoreboard extends uvm_scoreboard;

    `uvm_component_utils(scoreboard)

    uvm_analysis_export # (counter_trans)  ap_objseq_export;

    virtual Bus_if Bus_if1;

    scoreboard sb;

    local counter_subscriber counter_sub;

    rand bit store;

    function new (string name, uvm_component_parent="null");
            super.new(name, null);
    endfunction

    function void build_phase (uvm_phase phase);
            super.build_phase(phase);
            void'(uvm_config_db#(virtual Bus_if)::get(this,"*","Bus_if1",Bus_if1));
            if (!uvm_config_db#(virtual Bus_if)::get(this,"*","Bus_if1",Bus_if1))   begin
            `uvm_error("","uvm_config_db::get failed in Scoreboard");
            end
            ap_objseq_export = new(.name("ap_objseq_export"),.parent(this));
            counter_sub=counter_subscriber::type_id::create("counter_sub",this);
    endfunction

    function void connect_phase(uvm_phase phase);
            super.connect_phase(phase);
            ap_objseq_export.connect( counter_sub.analysis_export );
    endfunction

   task run_phase(uvm_phase phase);
    counter_trans req;
    if(Bus_if1.clk) begin
       if(!req.reset) begin
          sb.store = sb.store+1;
              end
          else begin
         sb.store = 0;
       end
    end
    if(sb.store==req.data) begin
       `uvm_info("","test has been passed","UVM_LOW");
        end
     endtask

endclass:scoreboard

//agent defination

class agent extends uvm_agent;

    `uvm_component_utils(agent)
    uvm_analysis_port # (counter_trans) ap_objseq;

    // virtual Bus_if Bus_if1;

    counter_sequencer        sqr;
    driver                   drv;
     monitor                         mtr;
    scoreboard               sb;
    coverage                 cov;
     counter_subscriber      count_sub;

    function new(string name, uvm_component_parent="null");
            super.new(name,null);
    endfunction

    function void build_phase(uvm_phase phase);
      super.build_phase(phase);
            ap_objseq = new(.name("ap_objseq"),.parent(this));
            drv = driver::type_id::create("drv",this);
            mtr = monitor::type_id::create("mtr",this);
            sb = scoreboard::type_id::create("sb",this);
            cov = coverage::type_id::create("cov",this);
            sqr = counter_sequencer::type_id::create("sqr",this);
    endfunction

    function void connect_phase(uvm_phase phase);
            super.connect_phase(phase);
            drv.seq_item_port.connect(sqr.seq_item_export);
            mtr.ap_objseq.connect(ap_objseq);
            ap_objseq.connect(cov.analysis_export);
    endfunction

endclass:agent

// environment defination
class environment extends uvm_env;
`uvm_component_utils(environment)

    agent agt;
    coverage cov;
    scoreboard sb;
    counter_subscriber counter_sub;

    function new(string name, uvm_component_parent="null");
            super.new(name,null);
    endfunction

    function void build_phase(uvm_phase phase);
    agt = agent::type_id::create("agt",this);
    cov = coverage :: type_id::create("cov",this);
    sb = scoreboard :: type_id::create("sb",this);
    counter_sub=counter_subscriber::type_id::create("counter_sub",this);
    endfunction

    function void connect_phase(uvm_phase phase);
            super.connect_phase(phase);
            agt.ap_objseq.connect(sb.ap_objseq_export);
            endfunction

endclass:environment

class test_count extends uvm_test;
`uvm_component_utils(test_count)

    environment env;

    function new(string name, uvm_component_parent="null");
            super.new(name,null);
    endfunction

    function void build_phase(uvm_phase phase);
            super.build_phase(phase);
            env = environment::type_id::create("env",this);
    endfunction

    task run_phase(uvm_phase phase);
                    counter_sequencer   v_sqr;
            phase.raise_objection(this);
              v_sqr = counter_sequencer::type_id::create("v_sqr",this);
              v_sqr.sqr = env.agt.sqr;
              v_sqr.start(.counter_sequencer( null ));
            #10ns
            phase.drop_objection(this);
    endtask

endclass:test_count

[dave_59]

In reply to babanrosesalluri5:

Please use code tags to make your code easier to read.

You seem to be confusing the concepts of a sequence and a sequencer in the code for counter_sequencer. I think you mean to have this as a sequence. or specifically as what is known as a virtual sequence that runs on the “null” sequencer.

[babanrosesalluri5]

In reply to dave_59:

Hi dave,

I had used code tags and reposted the code so once go through that and help me out. One more thing i said that i am new to this system verilog and uvm and i dont have much idea about virtual sequence, sequencer and start method. Why should we use v_sqr.start(.counter_sequencer(null)) in test class. As i told you that i followed uvm_tutorial_for_candy_lovers_master code to implement my counter code in uvm so i thought they used for that to initiate stimulus generation. Could you please guide me some documents so that i can gain more knowledge on this specific part in uvm.

Thanks in advance.