In reply to ce_2015:
Your approach is quite a diversion from using an approach like UVM with the use of classes instead of packages. I believe that you are better off using classes instead.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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Real Chip Design and Verification Using Verilog and VHDL($3) Amazon.com - Papers:
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Verification Horizons - March 2018 Issue | Verification Academy - SVA in a UVM Class-based Environment
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