Resulting sign and bit length using Conditional Operator

SystemVerilog
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1

Hi Forum Moderators,

I was trying the following code

 bit [1:0] a = 3, b = 3;
  
  initial begin
    $display("Addition result is 'd%0d",( 1 ? (a + b) : 0 ) );
    $display("Signed   result is 'd%0d",( 1 ? -4'sd4 : unsigned'(0) ) );
  end

As per Table 11-21 of LRM, for expression i ? j : k

Condition i (1) is self-determined whereas the bit-length of the expression is Max(L(j),L(k))

As 0 is 32-bits, (a+b) is calculated using 32-bits avoiding any possible overflow

(A) In the 2nd expression why is the result treated as unsigned ?

I expected Signed result is 'd-4 whereas I observe Signed result is 'd4294967292

(B) Is there any way to modify the 2nd statement which would ensure that unsigned nature of false condition doesn’t change the signed nature of true condition ?

Writing an if-else statement works.

Is there a possible solution using conditional operator ?

Thanks & Regards,

Aakash

2

An arithmetic expression that combines signed and unsigned types results in an unsigned type.

SystemVerilog resolves expression types before any evaluation; they cannot change dynamically.

Since the argument to a $display is self-determined, you need to provide a more comprehensive example that shows how you intend to use the result of that expression in a real-world context if you’re seeking a coding suggestion.

3

Hi Sir,

Taking inspiration from thread, I was trying to achieve int’( ) cast using 32’( ) cast and vice-versa ( edaplayground )

One difference between them is that unlike int’( ) cast, 32’( ) cast doesn’t change the state of the expression

Assuming that expression is always 2-state, I was able to achieve int’( ) using 32’( ) in both cases ( expression could be signed / unsigned )

However when expression is signed ( -4’sd4), I am observing unexpected results when achieving 32’( ) cast using int’( ) cast

(Q) Any suggestions ? Using if-else condition would work but wouldn’t be valid within with() clause of sum()

Could Implication operator → help ?

4

I’d forgotten about this: XY Problem Please take a step back and explain the problem you are trying to solve. Use words instead of SystemVerilog syntax.

5

As a coding practice I was trying to achieve size cast using type cast

Eg: Achieve 32’( expr ) using int’( expr ) ) where the expr is 2-state signed / unsigned