In reply to ben@SystemVerilog.us:
In reply to raviji:
Mot sure I understand your question. If, instead of dynamic ranges based on the value of a variable, you have a fixed static delay (e.g., 3) then
ap_a_sig: assert property(@ (posedge clk) $rose(a) |->
q_dynamic_repeat(a, duration) ##1 $fell(a));
// is equivalent to
ap_a_sig: assert property(@ (posedge clk) $rose(a) |->
a[*3] ##1 $fell(a));
// If you want to understand how the sequence q_dynamic_repeat(a, duration) works,
// you'll have to dig into the package and see its implementation.
I don’t understand your question design register gets mapped here as there is no hierarchy reference??
provide the link to the edaplayground
You’ll need to rephrase your requirements in English and ask what are you looking for, an assertion> a design question? I had to guess as to your intent.
In a single run of testcase, the value programmed from into the register X[7:0] is going to be fixed throughout, so ultimately the duration [2:0] shall also be fixed.
clk, a and b are part of interface to which the assertion shall be binded, but not the register bits, so how do those get mapped here to duration?
module top;
import sva_delay_repeat_range_pkg::*;
logic[7:0] x;
let duration = x[2:0]; // This is local to assertion usage, how does it map to the design register bits.
bit clk, a, b;
initial forever #10 clk=!clk;
ap_a_sig: assert property(@ (posedge clk) $rose(a) |->
q_dynamic_repeat(a, duration) ##1 $fell(a));
endmodule
The below one if implemeted has to be working for all 8 combinations a[*0] to a[*7] based on the register X [2:0] programming.
ap_a_sig: assert property(@ (posedge clk) $rose(a) |->
a[*3] ##1 $fell(a));
EDA Playground was to run the link example provided.