In reply to raviji:
In reply to ben@SystemVerilog.us:
Could you please explain it in a very simple way as I did not find any comments explaining the intent.
Mot sure I understand your question. If, instead of dynamic ranges based on the value of a variable, you have a fixed static delay (e.g., 3) then
ap_a_sig: assert property(@ (posedge clk) $rose(a) |->
q_dynamic_repeat(a, duration) ##1 $fell(a));
// is equivalent to
ap_a_sig: assert property(@ (posedge clk) $rose(a) |->
a[*3] ##1 $fell(a));
// If you want to understand how the sequence q_dynamic_repeat(a, duration) works,
// you'll have to dig into the package and see its implementation.
I also did not get how the design register gets mapped here as there is no hierarchy reference that the user needs to add to it.
I also tried running the same in EDA-Playground, but loop count 1000,1500 combinations are too high to execute them.
I don’t understand your question design register gets mapped here as there is no hierarchy reference??
provide the link to the edaplayground
You’ll need to rephrase your requirements in English and ask what are you looking for, an assertion> a design question? I had to guess as to your intent.