In reply to ben@SystemVerilog.us:
Thanks Ben to point to the link with an example.
Could you please explain it in a very simple way as I did not find any comments explaining the intent.
I also did not get how the design register gets mapped here as there is no hierarchy reference that the user needs to add to it.
I also tried running the same in EDA-Playground, but loop count 1000,1500 combinations are too high to execute them.