Register usage inside SVA to make Decision

SystemVerilog
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In reply to raviji:
Use my package SVA: Package for dynamic and range delays and repeats | Verification Academy
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Below is an example of usage. The package includes the usage of fixed and dynamic delays and repeats based on the value of a variable. The link also includes examples.


module top; 
    import sva_delay_repeat_range_pkg::*;
    logic[7:0] x; 
    let duration = x[2:0]; 
    bit clk, a, b;  
    initial forever #10 clk=!clk;  
    ap_a_sig: assert property(@ (posedge clk)  $rose(a) |-> 
                                   q_dynamic_repeat(a, duration) ##1 $fell(a));  
     
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
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    Real Chip Design and Verification Using Verilog and VHDL($3) Amazon.com
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