Register Access Automation

UVM
1

Hi,

I want to write a test for following:

→ For a register, write walking 1’s & 0’s, and check same behavior at RTL.
Here a register(32-bit) can have different field’s of different size & few bits reserved.
Similarly, there are about 20 different registers with different fields(in RAL) , each with multiple instances.

I wanted to write a test which is generic.

I was thinking of using an array for register & field names inside test. Or have a generic file outside the test with all info and using that form array’s inside your test.

Can you suggest any simpler way to implement this?

Thanks,
Rushil

2

In reply to RushilMithani_37:
Hi Rushil
UVM RAL model provides below predefined sequences to perform Registers attribute check

uvm_reg_access_seq - R/W permissions
uvm_reg_bit_bash_seq - Walking 1’s and 0’s
uvm_hw_reset_seq - Register reset values

I suggest you to use these sequences to to check Registers.

Thanks
Sreeni

3

In reply to chindanoor:

Hi ,
when we use uvm_reg_bit_bash_seq, does it verifies all the registers inside the provided reg block ??

when I used this seq , it was bit bashing only first register .
remaining registers were not bit bashed .
Why was this happening ?
Could you pls provide me solution for this .

Thanks,
Suguna

4

In reply to Suguna R:

This should work depending on how your registers are configured. For example, they need to be read/writable, Non-volitle.

5

In reply to Suguna R:

he source codes days:

// Class: uvm_reg_single_bit_bash_seq
//
// Verify the implementation of a single register
// by attempting to write 1's and 0's to every bit in it,
// via every address map in which the register is mapped,
// making sure that the resulting value matches the mirrored value.

This is what it is doing in your environment. Right.
If you want to do this on all registers you have to do this for all registers, running in a loop.

6

In reply to dave_59:

Some of the registers are read/write and read only …

Thanks,
Suguna

7

In reply to chr_sue:

Can u please provide me a example of using uvm_reg_single_bit_bash_seq .

Does uvm_reg_bit_bash_seq has a loop in it to parse through all registers in a given reg block??

Thanks,
Suguna

8

In reply to Suguna R:

Define your register sequence. It should contain:

mode_reg_block      your_regs;
uvm_reg regs[$]; // Queue of registers
uvm_reg_single_bit_bash_seq bash_seq;

task body();
   your_regs.get_registers(regs);
   regs.shuffle();
   foreach (regs[i]) begin
    bash_seq = uvm_reg_bit_bash_seq::type_id::create("bash_seq");
    bash_seq.model= your_regs;   //assign your regmodel
    bash_seq.start(your_sequencer);
   end
endtask

This is a piece of pseudo code, because I do not know your details.