Regarding forcing a value through sequence

UVM
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1

Hi All,

I am using uvm_hdl_force in my test environment. I was trying the same to assert/control the signal value from sequence, but didn’t succeed. Giving rtl path hierarchy in test environment or in test itself is pretty straight forward but I have no clue how to implement the same through sequence since we can’t give the rtl hierarchy in that. Any help on this please?

Regards,

2

In reply to pankajpattel:

See this link for some ideas as well as my DVCon paper which shows how to integrate a UVM testbench with a bound interface.