HI:
I notice REG:: in the uvm_reg_field.svh.
how to create the REG::?
In reply to birdluo:
You don’t create ‘REG::’, it is a namespace in the uvm_resource_db (or put another way, it’s part of the string scope argument when setting and reading the uvm_resource_db). If you look in the class reference manual, you will see that it is used to allow the user to exclude specific registers and (register) blocks from being tested when calling one of the uvm reg built in sequences (e.g. see UVM Class Ref 27.2 uvm_reg_hw_reset_seq).
In reply to birdluo:
Before giving you an explanation what it is and where it comes from could you please post a piece of code?
REG:: could be the scope resolution operator. And this will definitely not be created by the resource_db.
BTW it is not recommeded to use the resource_db. Use the config_db instead. The resource_db is the basic layer of the config_db.
In reply to chr_sue:
My apologies, I used the word ‘context’ when I meant ‘scope’, I have changed it my previous reply. I followed the convention of the Class Reference Manual (although I haven’t actually coded this for a couple of years). This is what the Class Ref Man uses:
uvm_resource_db#(bit)::set({"REG::",regmodel.blk.get_full_name(),".*"},"NO_REG_TESTS", 1, this);
To remove a register (gen_reg_0) from the test:
uvm_resource_db#(bit)::set({"REG::",regmodel.gen_reg_0.get_full_name()},"NO_REG_TESTS", 1, this);
thank you for your reply.
After I read the uvm code carefully, I think that the “REG::” is a string.
I thought that REG:: is Name spaces like package. So I misunderstand it.
In reply to birdluo:
string or namespace are not the alternatives. Because string is a data type and the namespace is something differently.
If you are using the config_db you don’t have the problem. You are using as the first argument ‘this’, which indicates a relative path. This makes your code reusable. The REG:: is hard-coded and does not allow to use this in another environment.