In reply to birdluo:
You don’t create ‘REG::’, it is a namespace in the uvm_resource_db (or put another way, it’s part of the string scope argument when setting and reading the uvm_resource_db). If you look in the class reference manual, you will see that it is used to allow the user to exclude specific registers and (register) blocks from being tested when calling one of the uvm reg built in sequences (e.g. see UVM Class Ref 27.2 uvm_reg_hw_reset_seq).