Reg and wire

SystemVerilog
,
1

Hi,
Wires in system verilog can be treated as physical interconnecting lines but regs that are used to store signal values cannot be treated as physical registers.Why not?
As reg is used inside in sequential blocks to hold output values just in the same way as in flip flops/registers , so why it cannot be treated as physical registers?

2

In reply to Shipra_s:

See What's the deal with those wire’s and reg’s in Verilog - Verification Horizons

3

In reply to dave_59:

Thanks Dave.