Reference signal name from parent module

SystemVerilog
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2

In reply to ricardosilvestre:
0

It is possible to do this creating a C function using SystemVerilog’s VPI.

int getParentName(char *user data) {
    vpiHandle system_h, arg_itr, in_h, , out_h, parent_handle;
    s_vpi_value out_s;
   // all this code just to get a handle to the function's argument
   // and without proper error checking
   sys_h = vpi_handle(vpiSysTfCall, NULL);
   arg_itr = vpi_iterate(vpiArgument, sys_h);
   in_h = vpi_scan(arg_itr);
   out_h = vpi_scan(arg_itr);
   // now get its parent net
   parent_h = vpi_get(vpiHighConn, in_h);
   // return the name of the net
   out_s.format = vpiStringVal;
   out_s.str = vpi_get_str(vpiName,parent_h);
   vpi_put_value(out_h,&out_s);
}

Inside your checker module you would call $getParentName(signal,name);

But it might be just easier to create a macro that instantiates your checker module

`define sigref_checker_inst(R,A,START,STOP,SIGNAL,REF) \
#(.reltol(R), \
  .abstol(A),\
  .startTime (START),\
  .stopTime(STOP),\
  ._signal(`"SIGNAL`"),\
  ._ref_signal(`"REF`")\
  )\
  chk1 (\
  .signal(SIGNAL),\
  .ref_signal(REF),\
  .enable_signal(1'b1)\
  );