Hello Verification Academy Forum Desk,
Today my query is on Reference Model. I just want to know in detail about my following question.
What is a Reference Model?
What are it’s significance in RTL/SoC Verification?
In reply to psp127143:
A reference model is something that was already implemented and have been verified/proven to meet the given specifications/standard/requirement. At times, it is also referred to as a golden model. They can be used in several ways. Few of them are:
- If the reference model is same as the IP/SoC you are trying to implement, then you can apply the same stimulus to your DUT and the model, to make sure that DUT response matches that of reference model. This helps verify your design quickly with less Test Bench infrastructure.
- In some cases, your DUT might be the master/host and might need to interact to slave/device which is not part of your system. In such cases, you can have this model instantiated as a slave/device in the TB along with the DUT to test the DUT’s handshake with the master/slave.
- In some cases, the third party processor/controller IP core’s in pretty huge SoC’s shall be replaced with the reference model (usually transaction based and not RTL) to help reduce simulation time and therefore fast verification closure.