Which would be a better approach for designing a reference model?
a. Is it better to be done with C-Based approach and include the reference model in the UVM-Scoreboard testbench and play with it using API’s ? OR
b. To simply try designing the reference model with the help of SV-OOPS based approach inside the UVM-Scoreboard and play with it ?
Note:__
Say for example wanted to write a reference model for a counter with different functionality mbed onto it !!
Kindly requesting people to give a better approach & solution !!
Thanks in Advance and would appreciate that !!
Desperado Trying to dig into UVM and travel deep inside
I think you will find a wide set of differing answers to this - there are many factors, and many personal choices.
Here are some to start the discussion.
Factors influencing reference model implementation choice:
(1) a pre-existing ‘gold’ reference model in one language/implementation or another - consider leveraging it as-is rather than rewriting it which risks adding new bugs.
Personal choices which come into play:
(2) for large model development, choose whichever language is the more natural choice for productivity AND maintainability for the person or team creating the model? I agree with the Janick Bergeron viewpoint on this: my favorite language is the one I’m not currently using. But reuse and maintainability should be considered also, if the model is to be adapted over time.
Please, others weigh in on your experiences and rationale for this choice …
I have used both C++/Matlab Golden Reference Model, which the Communication system guyz delivered. It was based on STL in C++ and used to provide me with the Vectors, both Input and output, for my TB to drive and compare to.
Implemented using the SV-DPI.
Pros:
C/Matlab functions/toolbox can be used straight away, reducing overall development time.
Performance simulation can be performed on this Golden Reference Model.
Cons:
Extra learning curve added, if you are not familiar with the new languages involved.
Initial bring-up, integrating the two worlds, with/without tool support, takes considerable time.
Said this, I have also developed Golden Reference Model developed in SV-UVM, which drived the DUT and sampled the output from the same and compared to one generated by my SV-UVM.
Pros:
No new language needs to be learned and past experiences can be utilized in developing the Golden reference Model.
As using SV-UVM, RTL engineers and verifiers can also debug.
Can embed assertions during development.
Cons:
Implementing complex functions may take some time, as against the ones available with C++/Matlab.
@Gordon: Thanks a ton for your inputs and initiating the response !
@Vipra: Thanks to you for listing out your experience, pros& cons ! Pretty useful.
a. Well my case now is like, actually wanted to verify a counter design… So thought of reference model based verification approach…
b. So I actually don’t have any previous reference model which I can use it straight away in my testbench.
So I thought of creating one and that’s where I ended up with this question ?? because I knew quite a lot of people develop reference model using System-C or C or Matlab based approach but since I was pretty comfortable with SV-UVM based approach.
I was like why can’t I design my reference model with the language I know (i.e. SV-UVM) !! As Vipra listed, its has design features and as well the use of OOPS !!
As Gordon listed, it would be great if more people share there experience and help me out on this !!
Here’s one possible approach:
Staying within SV should be your default choice for coding a new reference model where one does not already exist… unless some requirement arises during your initial design work, that makes a C or other foreign model a better choice.
The OOP features and data structures within SV are sufficient for most purposes.
…and the flip side:…
Reasons to switch away from that default might be a requirement to write lots of new SV code to implement standard algorithms or more complex data structures, e.g. file/parsing, sorting algos, that may be available off the shelf in C. Note that performance is not normally a big concern either way but you should know where the bottleneck lies in your TB performance.
Counters?
They are usually pretty control-oriented, predictable functions, easy to model in SV. For any counter design I can think of (whether it’s a simple realtime clock or a complex software-radio-timing-algorithm for GSM/UMTS/LTE), I’m probably going to choose SV 99% of the time, unless I need a whole off-the-shelf matlab UMTS/LTE model anyway for something bigger than just the counter part.
WoW !! Thanks Gordon !! Appreciate that !! Will go ahead applying SV-UVM based approach for the reference model design !! Do you have any sample SV-UVM based reference design ? If possible can you post the same…
You can also make use of a lot of C/C++ library functions from SV via the DPI. This should reduce the requirement to re-code any supporting libraries that you might need.
I Have implemented “DPI” Environment and verified our design with directed test cases. As now “UVM” takes place as advanced methodology in verification we are thinking to migrate our verification to next level like build a verification environment using “UVM”. I have some queries like
The golden reference is in langauge "C"so I am not thinking to develop reference model in UVM to avoid development time. if i want to use c reference model in UVM how can i add it…can you people give any example plz. UVM-SV example where i can import c reference in UVM environment.
Which is the best way to implement test cases in “C” or in “UVM”.
What is the advantage to build a environment in “UVM” where as the design has been tested with directed test cases at maximum extent in “DPI”
Your contribution is a little bit confusing because you are using the terms DPI and UVM in a wrong relationship.
To clarify:
(1) DPI stands for ‘Direct Programming Interface’ and is a capability of SystemVerilog and not a language.
(2) UVM is a methodology and a base class library based on SystemVerilog.
The question is which language is used for your current testbench. Please specify.
Current test bench is in “DPI”. The reference model is in “C” so if i want to use same reference model in UVM and send stimulus from UVM to DUT as well as to reference model, collect output and verify in UVM score board how can i access “C” reference model in UVM. post example code for accessing reference model in UVM.
Again, a testbench cannot be written in “DPI”. It might be written in Verilog, SystemVerilog or VHDL.
I guess you have a testbench written in SystemVerilog, because the DPI belongs to SystemVerilog.
Because UVM is based on SystemVerilog you can use the DPI in the same way as you do in your SystemVerilog testbench.