Reference Model Design ! C-Based or Can it be done with the SV-OOPS Based ? Which would be better approach?

UVM
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In reply to babanrosesalluri5:

Again, a testbench cannot be written in “DPI”. It might be written in Verilog, SystemVerilog or VHDL.
I guess you have a testbench written in SystemVerilog, because the DPI belongs to SystemVerilog.
Because UVM is based on SystemVerilog you can use the DPI in the same way as you do in your SystemVerilog testbench.