Record two diff CLK's posedge's $time when coincide and not

SystemVerilog
1

I have 2 clock, clk_a, clk_b[3:0]. clk_b has 4 phases and each differs a bit.

Now i want to record and compare the time difference between
clk_b[0] and clk_a,
clk_b[1] and clk_a,
clk_b[2] and clk_a,
clk_b[3] and clk_a.

Then using this difference to compare with the reference value. They should be the same.

This is done using a fork…join. //code later

Most of the time, the clk_b[i] does not coincide with clk_a, and everything is fine.

When they do coincide, e.g. posedge clk_b[0] coincide with posedge clk_a, their time difference should be zero, ref. time difference is zero. But I cannot get $time to record clk_b[0]'s time at that very same posedge. $time will always record the next posedge, which is wrong for my design.

Below is my code to give you guys a better picture:


//some code

@(posedge clk_a);//wait a posedge

fork
    begin
      @(posedge clk_a);//desired logic: when clk_a posedge happens, record the time of the next clk_b[0] posedge
      @(posedge clk_b[0])//IF clk_b[0] posedge coincides with clk_a posedge, record time of this very coincided posedge. 
      time_b[0] = $time;//My code now sadly is recording the next clk_b[0] posedge after the coincided one.
    end
    begin
      @(posedge clk_a);
      @(posedge clk_b[1])
      time_b[1] = $time;
    end    begin
      @(posedge clk_a);
      @(posedge clk_b[2])
      time_b[2] = $time;
    end    begin
      @(posedge clk_a);
      @(posedge clk_b[3])
      time_b[3] = $time;
    end
join_none
    begin
      @(posedge clk_a)//record time when clk_a posedge happens
      time_a = $time;
    end

Would appreciate any thoughts.
Thanks guys.

2

In reply to tyyang:
How about writing your code assuming clk_a could come before or after clk_b[n].

@(negedge clk_a);//wait for some edge that comes before any of the posedge clk_b's 
fork
      @(posedge clk_b[0]) time_b[0] = $time;
      @(posedge clk_b[1]) time_b[1] = $time;
      @(posedge clk_b[2]) time_b[2] = $time;
      @(posedge clk_b[3]) time_b[3] = $time;
      @(posedge clk_a)    time_a = $time;
join

This code, as well as your original example assume that the frequency of all the clocks are the same.

Also, be careful using $time as the time precision will be truncated.

3

In reply to dave_59:

Hi Dave, thanks for the input. But in fact the two clock are not the same, their posedge only coincides a few times, i.e. falls on the exact time, and it is these few times that I want to capture and correctly record their difference as zero.

Thanks,
Jack

4

In reply to tyyang:
Then you are going to have to explain better how the code is supposed to know when the clocks coincide and perform the check. The problem is in Verilog there is no such thing as two event occurring simultaneously - they would always be in a race. And depending on how the code was written to generate the clocks, there could be skew to make the difference in time non-zero.
You probably should look at using an assertion to do this check, but the assertion would still need to know when both clock edges are expected to coincide.