Record two diff CLK's posedge's $time when coincide and not

SystemVerilog
2

In reply to tyyang:
How about writing your code assuming clk_a could come before or after clk_b[n].

@(negedge clk_a);//wait for some edge that comes before any of the posedge clk_b's 
fork
      @(posedge clk_b[0]) time_b[0] = $time;
      @(posedge clk_b[1]) time_b[1] = $time;
      @(posedge clk_b[2]) time_b[2] = $time;
      @(posedge clk_b[3]) time_b[3] = $time;
      @(posedge clk_a)    time_a = $time;
join

This code, as well as your original example assume that the frequency of all the clocks are the same.

Also, be careful using $time as the time precision will be truncated.