Realtime rounding in assertion

SystemVerilog
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1

I am having the hardest time figuring out how realtime boolean expression rounding occurs. Given the following code:


`timescale `1ns/1fs
`define CLK350_PERIOD_L 2.857000ns
`define CLK350_PERIOD_H 2.857286ns

property p350Mhz(clk); 
   realtime current_time;
   @(posedge clk)      
   (1,current_time=$realtime) |=> (`CLK350_PERIOD_L <= $realtime-current_time && $realtime-current_time <= `CLK350_PERIOD_H);
endproperty

Into this property, I am passing in a clock whose period measures 2.857ns exactly (from sim waveform set at fs scale). However the assertion continues to fail despite the fact that 2.857ns should fall with the _L and _H macros that I have specified…

I have also tried dividing all $realtime calls by 1fs:


property p350Mhz(clk); 
   realtime current_time;
   @(posedge clk)      
   (1,current_time=$realtime/1fs) |=> (`CLK350_PERIOD_L <= $realtime/1fs-current_time && $realtime/1fs-current_time <= `CLK350_PERIOD_H);
endproperty

Does the boolean expression $realtime-current_time get rounded somehow due to timeunit? How can I get the assertion to not fail?

2

In reply to ce_2015:

Equality is difficult to achieve when using real numbers.

See Why 0.1 Does Not Exist In Floating-Point - Exploring Binary

3

In reply to dave_59:

But I’m just trying to do less than or equal to/greater than or equal to… not exact equality…

Is there a better recommendation for verifying clock frequency tolerances with assertions?

4

In reply to ce_2015:

You are in the equal part of “less than or equal”. You should work in ps to remove any rounding errors or adjust your values away from equal. i.e.

`define CLK350_PERIOD_L 2.85699ns