Range must be bounded by constant expressions

SystemVerilog
1

I am trying to implement the following in systemverilog.

always_comb
    begin
	for(int i=0;i<=124;i=i+6)
	    begin
	        offset = DFF_data[ ((2*i)+1):(2*i) ]; // Error !	
		data_output[i+offset]= data_input[i];
	    end
   end

I get the following error in the line marked above: Range must be bounded by constant expressions. I can see the error ocuurs beacuse of the use of “i” in defining the range of array DFF_data. But writing this without “i” seems impractical. I am using QuestaSim 10.1d. Has anyone come across such a situation?