How to access a slice with a dynamic value in SystemVerilog?

SystemVerilog
1

I want to access a slice with a dynamic value. I have tried to do it in different ways. In the first case reducing the logic of the module for the control of the index value etc, verilator told me that it is not a constant value and I agree with that and then I change for the second version but I got the same result.

module m1 (
input  logic [1:0] in1,  // 8-bit input vector 1
input  logic [4:0] in2,  // 8-bit index
);
logic not_cero;

always_comb begin
 not_cero = in2[in1[1:0]:0] != '0;
end
//more logic
endmodule

Also, I tried:

module m1 (
input  logic [1:0] in1,  // 8-bit input vector 1
input  logic [4:0] in2,  // 8-bit index
);
logic not_cero;

always_comb begin
for (int i = 0; i < 4; i++) begin
 if((in1[1:0]) == i)begin
 not_cero = in2[in1[i:0]:0] != {i{1'b0}};
end
end
end
//more logic
endmodule

But I have the same compilation error:
First value of [a:b] isn’t a constant, maybe you want +: or -:
I tried to change the operand to [0*i:i], but I got another constant error.

Any ideas on how to implement this logic?

2
3

Good morning Dave,

Thank you for your help, but I think the post that you share with me doesn’t open my mind in order to see how can I build the logic that I want it.

Because in my case I need to cover all possible slices in that can be carried for in1, and then I don’t know why my second version doesn’t work.

I am working on it.

4

A simple shift works in your case

always_comb begin
 not_cero = ( in2 << ( $bits(in2)-in1) ) != '0;
end

Note that parenthesis are not needed, but I find it makes it easier to read.

5

Thanks, Dave this works well for the logic that I want to do.