Getting The range of the part select is illegal Error

Hi ,

for(int i = 0; i<15; i++) begin
     if( value inside {[(4*i):((4*i)+3)]})
         data[45:14] = **temp_data[((i*32)+31):(i*32)**];
 end

I’m getting the below error while splitting the temp_data width
Error signature:
The range of the part select is illegal

Please help me on this.

Hi dave… i could not understand your implementation.
My expectation is
if ( value inside {[0:3]})
data[45:14] = temp_data[31:0];
else if (value inside {[4:7]})
data[45:14] = temp_data[63:32];



else if (value inside {[56:59]})
data[45:14] = temp_data[479:448];

How to simplify this .Please help me on this.

If you only want the first match to make the assignment, use a break within the loop.

for(int i = 0; i<15; i++)
     if( value inside {[(4*i):((4*i)+3)]}) begin
         data[45:14] = temp_data[i*32+:32];
         break;
     end

Thank you deve. it’s working.
may i know difference between below items
temp_data[((i*32)+31):(i*32)] ---- > for this i got The range of the part select is illegal error
temp_data[i*32+:32] ----> this is working fine

both are doing part selection. i could not understand the difference.

The difference has to do with the compilation flow. SystemVerilog is based on a fixed type system where the width of variable/expression is part its type. It needs the type to generate the right calculations for evaluating expressions. The compiler cannot calculate the width if either [lindex:rindex] includes a variable. The [pos+:width] syntax allows a variable, but the width still needs to be a constant expression.

Thank you for your explanation!