Randomize list with constraints

SystemVerilog
,
3

In reply to stupidkris1010:

It would be much easier to write this as a packed array instead of an unpacked array.


module top;
  bit [31:0] list;
  int unsigned shift;
  initial repeat (50) begin
    randomize(list,shift) with {
      list == (32'b1 << shift) -1;
      shift <=32; };
    $display("%5d %b",shift, list);
  end
endmodule

I can’t really say which is more efficient in terms of performance.