Randomize list with constraints

SystemVerilog
,
1

Hi all,

I am learning SystemVerilog right now. I want to understand randomize() method by implementing the following:

→ Generate a random array of 32 bits with following constraints:

  • There are no 0’s in between 1’s.
  • if it is a nonzero value, the LSB must be 1
  • Example : 0x00000000, 0x00000001, 0x00000003, 0x00000007, 0x0000000F … 0xFFFFFFFF

Can someone help me with right constraints?

Thanks.

2

In reply to stupidkris1010:

I am using this one which works fine, but looking for comments to optimize it further/ find other efficient way:


task randomize_list;
    bit list[];
    list  = new[32];
    $display("Random list:\n");
    randomize(list) with { 
      list.sum < 32;
      foreach(list[i]) if(i>0 && list[i]) list[i-1] != 1'b0;
    };
    for(int i=0;i<32;i++)
      $display("%1b", list[i]);
        
  endtask
3

In reply to stupidkris1010:

It would be much easier to write this as a packed array instead of an unpacked array.


module top;
  bit [31:0] list;
  int unsigned shift;
  initial repeat (50) begin
    randomize(list,shift) with {
      list == (32'b1 << shift) -1;
      shift <=32; };
    $display("%5d %b",shift, list);
  end
endmodule

I can’t really say which is more efficient in terms of performance.

4

In reply to dave_59:

Surely it is much easier. Thanks for providing this solution :)