Randomization Failure

SystemVerilog
, ,
1

Hi All,
I have an 8-bit vector in this vector I need to get continuous ones in four places, e.g., 00111100, 11110000, 00001111 like this.
I have written a constraint for the above question, But I am seeing a randomization failure Can anyone help why my constraint is conflicting?


module top;
  class ones;
    rand logic [7:0] a;
    rand int unsigned b[4];
    constraint	c	{
      solve b before a;
      foreach(b[i])
      {
        
        if(i != 0)
        {
          b[i] inside	{[0:7]}; //Constraining helper array values in between 0 to 7
          b[i] == b[i-1] + 1; // current array value is greater than previous array value + 1
        }
          else
          {
            b[i] inside	{[0:7]};
          }
        foreach(a[j])
        {
          if( j == b[i])
            a[j] == '1;
          else
            a[j] == '0;
          
        }
      }
        
      
    }
        
        
  endclass
  
  initial
    begin
      ones o;
      o = new();
      assert(o.randomize());
      $display("%p, %b", o.b, o.a);
    end
endmodule

run -all

** Warning: License feature ‘svverification’ will expire today.

testbench.sv(51): randomize() failed due to conflicts between the following constraints:

testbench.sv(13): c { (b[1] == (b[(1 - 1)] + 1)); }

testbench.sv(17): c { (b[0] inside { [0:7] }); }

testbench.sv(22): c { if ((7 == b[0])) {a[7];} }

testbench.sv(22): c { if ((7 == b[1])) {a[7];} }

testbench.sv(22): c { if ((6 == b[1])) {a[6];} }

testbench.sv(22): c { if ((5 == b[1])) {a[5];} }

testbench.sv(22): c { if ((4 == b[1])) {a[4];} }

testbench.sv(22): c { if ((3 == b[1])) {a[3];} }

testbench.sv(22): c { if ((2 == b[1])) {a[2];} }

testbench.sv(22): c { if ((1 == b[1])) {a[1];} }

testbench.sv(24): c { if ((!(7 == b[0]))) {(~a[7]);} }

testbench.sv(24): c { if ((!(6 == b[0]))) {(~a[6]);} }

testbench.sv(24): c { if ((!(5 == b[0]))) {(~a[5]);} }

testbench.sv(24): c { if ((!(4 == b[0]))) {(~a[4]);} }

testbench.sv(24): c { if ((!(3 == b[0]))) {(~a[3]);} }

testbench.sv(24): c { if ((!(2 == b[0]))) {(~a[2]);} }

testbench.sv(24): c { if ((!(1 == b[0]))) {(~a[1]);} }

testbench.sv(24): c { if ((!(7 == b[1]))) {(~a[7]);} }

Given:

bit [31:0] b[0]

logic [7:0] a

bit [31:0] b[1]

** Note: (vsim-7130) Enabling enhanced debug (-solvefaildebug=2) may generate a more descriptive constraint contradiction report and -solvefaildebug testcase.

** Note: (vsim-7106) Use vsim option ‘-solvefailtestcase[=filename]’ to generate a simplified testcase that will reproduce the failure.

** Warning: (vsim-7084) No solutions exist which satisfy the specified constraints; randomize() failed.

Time: 0 ns Iteration: 0 Process: /top/#INITIAL#47(#ublk#31584#48) File: testbench.sv Line: 51

** Error: Assertion error.

Time: 0 ns Scope: top File: testbench.sv Line: 51

'{0, 0, 0, 0}, xxxxxxxx

exit

2

In reply to marathuteja:
https://verificationacademy.com/forums/systemverilog/how-write-constraint-generating-continuous-mask#reply-91871

3 

class ones;
    rand logic [7:0] a;
 
    constraint	a_count4{
      $countones(a) == 4;
    }     
 
 
  endclass
4

In reply to MageshV:

That does not handle consecutive 1’s

5

In reply to marathuteja:

please check here

Thanks,
Juhi Patel