Randomising a logic vector of more than 32 in System Verilog

In reply to dave_59:

Thanks Dave. I will try out both methods.

Any idea on why SV finds it “difficult” to randomize the 93 bits using randc, after constraining first three bits constant ?? I mean, if that constraint is not there, SV can cycle thru all 96-bit values in unique fashion. Then it should be able to cycle thru 93-bit values as well. And now I really doubt whether it is actually cycling thru 96-bit values, when I think about the memory limitations on randc mentioned in LRM.