Randomising a logic vector of more than 32 in System Verilog

[dave_59]

In reply to Mitu Raj:

Yes, there will be lots of overhead for this if you expect to generate millions of random packets.

However, if you know that you only need 2²⁴ (10 million) unique vectors out of 2⁹⁶ possible vectors, you can limit the uniqueness to 24 bits.

class Config ;
   rand vec_config pkt ;
   randc bit [95:72] uniq;
 
   constraint pr_constr {
                         if (condition)  { pkt.pr [2 : 0] <= '1 ;};
                        }
   constraint un_constr {
                        pkt[95:72] == uniq;
                        }
endclass